1. Field of the Invention
The present invention relates to an MOS semiconductor memory device, more specifically, to a semiconductor memory device such as a dynamic random access memory. RAM, having a plurality of memory cell matrices and a sense control for controlling operations of sense amplifiers connected to the matrices.
2. Description of the Prior Art
Some conventional types of MOS semiconductor memory devices include a plurality of memory cell matrices arranged with associated sense amplifiers and sense controls provided. In such types of device, since each memory cell matrix has a sense control provided exclusively, the number of constituent elements and hence that of wirings therebetween are increased, which has been a hindrance to designing highly integrated memory devices.
Heretofore, there has been an MOS semiconductor memory device of the type shown in FIGS. 2A and 2B, for example. A description will be given of the constitution of the device with reference to those figures, which illustratively show schematic configurations of the conventional MOS semiconductor memry device.
The illustrative device is a dynamic RAM including memory cell matrices 10-1 to 10-4 into which memory cells are grouped in accordance with row and column addresses. Each of the memory cell matrices 10-1 to 10-4 comprises a plurality of memory cells 13 of a single-transistor type connected to word lines 11 and to pairs of bit lines 12a and 12b, and a plurality of noise cancellers 15 each including an MOS tansistor connected to a dummy word line 14 and a pair of bit lines 12a and 12b.
In the proximity of the memory cell matrices 10-1 to 10-4, there are disposed in association therewith row address decoders 20-1 to 20-4, word line drives 21-1 to 21-4, and noise canceller controls 22-1 to 22-4, respectively. The drives and controls are connected to the associated decoders. For the work line drives 21-1 to 21-4 and the noise canceller controls 22-1 to 22-4, the voltages thereof are increased by use of a word line votage step-up or booster circuit 23. The word line drives 21-1 to 21-4 are connected to the respective memory cell matrices 10-1 to 10-4, whereas the noise canceller controls 22-1 to 22-4 are linked to the dummy word lines 14.
Connected between the bit lines 12a and 12b is an n-channel type of sense amplifier 24 and a p-channel type of sense amplifier 25. Those sense amplifiers 24 and 25 are respectively connected via associated enable signal lines 26 and 27, an n-channel type of MOS transistor 29 to sense controls 30-1 to 30-6. The sense controls 31-1 to 31-6 are respectively selected in response to address signals Al, . . . , Ai, . . . , Aj, . . . , and An; specifically, based on the signals Ai and Aj and inverted signals thereof Ai and Aj. These controls are connected in common via a word line monitor curcuit 31 to the word line booster circuit 23.
In FIGS. 2A and 2B, lines 30S and 30S are complementary outputs from the sense controls 30-1 to 30-6, Vcc indicates a power supply voltage, and Vcp denotes a reference voltage which is equal to Vcc/2.
FIGS. 3A to 3G plot operative waveforms appearing in the system of FIGS. 2A and 2B. Referring to those waveforms, operations of the circuitry shown in FIGS. 2A and 2B will be described. In a memory cell matrix, 10-1, for example, selected based on address signals A1 to An, the word line drive 21-1 is supplied with outputs from the word line booster circuit 23 and the row address decoder 20-1 to resultantly produce an output. Based on the output, a word line 11 is selected to be set to its high level "H". In this situation, on the all bit lines connected to the all memory cells 13 linked to the word line 11, namely, the selected bit lines 12a, noises appear because of coupling of word line 11 caused by parasitic capacitance. In order to suppress the noises, the noise canceller control 22-1 receiving the outputs from the row address decoder 20-1 and the word line booster 23 produces an output to set the dummy word line 14 to its low level "L". In response thereto, the noise canceller 15 is enabled. The bit lines 12b not connected to any memory cell 13 is called unselected bit lines.
If information stored in a memory cell 13 is a logical "1", for example, when the word line 11 carries a potential level not less than the sum of reference potential Vcp and NMOS threshold potential VTN, a potential difference .DELTA.V (=.vertline.selected bit line 12a potential-unselected bit line 12b potential.vertline.) appears between the selected bit lines 12a and 12b. If information stored in the memory cell 13 is a logical "0", the potential difference is developed when the level of the word line 11 becomes at least the voltage VTN.
In order for the potential difference .DELTA.V to be fully developed, the word line monitor 31 receiving the output from the word line booster 23 supplies an output with a predetermined delay time to a sense control, 30-2 in this example, associated with the selected memory cell matrix 10-1. The sense control 30-2 is beforehand selected in response to the address signals AiAj to AiAj. The sense control 30-2 supplied with the output from the word line monitor 31 sets one output 30S therefrom to its high level "H" and the other output 30S to its low level "L". When the ouptut 30S is thus set to the high level, the MNOS 28 turns on and hence the enable signal line 26 goes down to its low level "L", which is identical to a ground potential. When the output 30S is thus lowered, the PMOS 29 turns on to set the enable signal line 27 to its high level "H", which is equal to the power supply potential Vcc. Consequently, the n-channel type of sense amplifier 24 and the p-channel type of sense amplifier 25 start their operations. This initiates charge and discharge operations of the paired bit lines 12a and 12b. When the levels of the bit lines 12a and 12b are resultantly settled, the sense operation is completed.
Information signals on the bit lines 12a and 12b are passed via a transfer gate, not shown, which turns on and off in response to an output from a row address decoder, so as to be read out to an external device over a line such as a data bus.
However, in the apparatus configured as above, since the exclusive sense controls 30-1 to 30-6 are respectively required for the memory cell matrix pairs 10-1 and 10-2 as well as 10-3 and 10-4, the number of circuit constituent elements and hence the number of wirings therebetween are increased, which is not suitable for a high integration of the device. In addition, solutions of these problems have been attended with difficulties.